COOLMOS

In the conventional VDMOS device structure, there is a contradictory relationship between Rdson​ and BV. To increase BV, the doping concentration of the epi-layer is usually reduced. However, the epi-layer also serves as the path for forward current flow. A lower doping concentration in the epi-layer inevitably leads to higher resistance and thus a larger Rdson​. Rdson​ directly determines the power loss of a single MOSFET. For conventional VDMOS, this contradiction cannot be reconciled, which constitutes its inherent limitation. This is not the case for CoolMOS. By introducing a P-region that extends deep into the epi-layer, BV is greatly improved without affecting Rdson​.

 

In conventional VDMOS, reverse voltage withstand capability mainly relies on the PN junction at the interface between the N-type epi-layer and the body region. For a PN junction under reverse bias, voltage is sustained by the depletion region, depending on the electric field intensity and the expanded width of the depletion region. In conventional VDMOS, the doping concentration of the P-body is higher than that of the N-epi-layer. As is known, the depletion region of a PN junction mainly expands toward the lightly doped side. In this structure, the depletion region expands very little on the P-body side and contributes almost nothing to voltage sustaining. Voltage is mainly borne by the N-side region between the P-body and N-epi-layer, where the electric field intensity varies gradually and peaks near the PN junction surface.

 

In the CoolMOS structure, a P-region with lower doping concentration than the P-body is adopted. As a result, the depletion region on the P-side expands significantly and penetrates deep into the epi-layer, enabling both sides of the PN junction to withstand high voltage. In other words, the peak electric field Ec​ is shifted from near the device surface toward the inner region of the device.

 

 

 

Since the Rdson​ of SJ-MOS is much lower than that of VDMOS, the conduction loss of SJ-MOS in power supply systems is significantly reduced. This greatly improves the conduction loss performance of individual MOSFETs in system products and enhances overall efficiency. This advantage is especially prominent in high-power, high-current power supply applications.

 

 

Firstly, at the same current and voltage ratings, the die area of SJ-MOS is smaller than that of conventional VDMOS. This allows manufacturers to package devices in smaller volumes for the same specifications, helping to increase the power density of power supply systems.

 

Secondly, the lower conduction loss of SJ-MOS reduces heat generation in power supplies. In practice, heat sinks are often used to control the temperature rise of MOSFETs within a suitable range. Since SJ-MOS generates less heat, the required heat sink size can be reduced. For lower-power supplies, heat sinks can even be eliminated entirely, effectively improving the power density of the system.

 

 

Conventional VDMOS has a relatively large gate charge. In practical applications, temperature rise issues often occur due to insufficient driving capability of control ICs. To ensure fast turn-on of MOSFETs, push-pull or other dedicated driver circuits must be added in some designs, increasing circuit complexity. SJ-MOS features smaller gate capacitance, which lowers the demand for driving capability and improves the reliability of the system.

 

 

Structural improvements in SJ-MOS significantly reduce its output junction capacitance, thereby lowering losses during turn-on and turn-off. Meanwhile, the reduced gate capacitance shortens the charging time, greatly increasing the switching speed of SJ-MOS. For fixed-frequency power supplies, this effectively reduces switching losses and improves the efficiency of the entire power system. The effect is particularly pronounced in high-frequency power supplies.